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V96SSC Rev. B1
HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960(R)Sx/Jx AND PowerPCTM 401Gx PROCESSORS
* Direct interface to i960Sx/Jx and PPC401Gx processors * High-performance burst DRAM controller * Two-channel fly-by DMA controller * Serial communications unit * Programmable chip-select/strobe generation * Support for 8/16-bit boot PROMs * Two 32-bit general purpose timers * Pulse width modulation capability * System watchdog and heartbeat timers * 16 general purpose I/O bits * Eight input ports and eight output ports * Interrupt control unit * Local bus speeds up to 33MHz * Low cost 100-pin EIAJ PQFP package * Fastest time to market for i960Sx and i960Jx based designs
The V96SSC High-Integration System Controller is a single-chip device that simplifies the design of systems based on i960Sx, i960Jx or PPC401Gx embedded microprocessors. The V96SSC replaces many lower integration components with a single, high-integration device. Nearly all i960 or PowerPC processor based systems will require DRAM for code and data storage. The V96SSC includes a highperformance DRAM controller which is programmable to accommodate a wide range of DRAM speeds and architectures. The eight chip-select/strobes further simplify peripheral/memory connection. Each select has programmable timing and a total of four waitstate generators are provided.
Beyond simplifying memory and peripheral control, the V96SSC also includes many of the peripherals needed to build a high-performance i960 or PPC401Gx based system: DMA channels, synchronous/asynchronous serial port, general purpose and system heartbeat timers, bit I/O ports, and an interrupt controller. In addition, the V96SSC includes special features to enhance system integrity. The bus watch timer prevents system hangs on access to unpopulated memory. A watchdog timer is also included to recover from software upsets. Due to its small footprint, and glueless interface, the V96SSC provides the best features of an integrated processor without any performance compromises!
i960Sx/Jx PPC401Gx CPU
IRQs
V96SSC
SYSTEM CONTROLLER
ADDR
DRAM ARRAY
PROM
LOCAL BUS
LOCAL BUS LOCAL LOCAL BUS BUS
DMA REQUEST
V960PBC or V961PBC PCI BRIDGE CONTROLLER
NETWORKING
CHIP SELECTS AND STROBES
DEVICE
PCI BUS
Copyright (c) 1997, V3 Semiconductor Corp. V96SSC Data Sheet Rev 2.3
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V3 Semiconductor reserves the right to change the specifications of this product without notice. V96SSC and V96xPBC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
V96SSC
This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V96SSC. Detailed functional information is contained in the User's Manual. V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.
1.0 Product Codes
Table 1: Product Codes
Product Code Processor i960SA/SB i960JA/JD/JF PPC401GF Bus Type 16-bit multiplexed 32-bit multiplexed 32-bit multiplexed Package Frequency
V96SSC-33LP
100-pin EIAJ PQFP
33MHz
2.0 Functional Description
The V96SSC consists of the following functional units: * * * * * * * * * Direct i960 and PPC401Gx Processors Bus Interface Unit Burst DRAM Controller DMA Controller Serial Communications Unit Chip Select/Strobe Unit General Purpose Timer/Counters System Watchdog and System Heartbeat Timers Interrupt Control Unit I/O Control Unit and Internal Signal Multiplexer
A block diagram of the V96SSC is shown in Figure 1. Each of the functional units is described briefly in the sections below. The V96SSC Data Sheet provides information regarding AC and DC specifications, pinout, and packaging. Detailed information regarding hardware and software interfacing can be found in the V96SSC User's Manual.
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Figure 1: V96SSC Block Diagram
A31,A[26:16] AD[15:0] BE[1:0] ADS ALE BLAST W/R BTYPE[1:0] HLDA HOLD INT RESOUT RESET CLK2 i960 PROCESSOR INTERFACE DRAM CONTROL MA[11:0] RAS[1:0] CAS[3:0] WE OE[1:0] LE
I/O MUX and BIT I/O
I/O[15:0]
BUS WATCH SYSTEM HEARTBEAT/ WATCHDOG TIMERS SERIAL COMM UNIT
TWO CHANNEL DMA 32-BIT TIMERS (2) CHIP SELECT STROBE LOGIC
DREQ0 DACK0 DREQ1 DACK1
2.1
Direct i960 Sx/Jx and PPC401Gx Processors Bus Interface Units
The V96SSC is designed to connect directly to i960Sx/Jx and PPC401Gx processors. No "glue logic" is required. Care was taken during the design of the V96SSC to insure full AC timing compatibility with these processors running with bus speeds up to 33MHz. Even the pinout of the V96SSC has been designed with ease of connection in mind. At the beginning of each processor bus cycle the V96SSC samples the BTYPE[1:0] pins. As it's shown in the following table, these pins indicate what type of bus cycle is being run. Because the bus type is dynamically detected, the V96SSC may be used in systems using both 16-bit and 32-bit masters.
Table 2: BTYPE[1:0] Pin Decoding BTYPE[1:0] 00 CPU Mode i960SA/SB Boot Address A[31, 26:24]="0000" Description 16-bit data bus, BE[1:0] valid for current cycle, both processor and V96SSC use 2x clock 32-bit data bus, BE[3:0] valid for current cycle, processor uses 1X clock and V96SSC uses 2X clock
01
PPC401Gx
A[31, 26:24]="1111"
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Table 2: BTYPE[1:0] Pin Decoding BTYPE[1:0] 10 CPU Mode i960Jx (32 bit bus) i960Jx (16 bit bus) Boot Address A[31, 26:24]="1110" Description 32-bit data bus, BE[3:0] valid for current cycle, processor uses 1X clock and V96SSC uses 2X clock 32-bit data bus, BE3 and BE0 valid for current cycle, processor uses 1X clock and V96SSC uses 2X clock
11
A[31, 26:24]="1110"
In i960Sx systems, the low order address signals are latched internally from the AD[15:0] bus upon assertion of ALE. The high-order address lines are demultiplexed on the i960Sx processor, and are routed directly to the V96SSC's high order address inputs. The i960Jx processor uses a 32-bit multiplexed address/data bus, therefore for i960Jx bus accesses, the V96SSC latches the high order address signals internally on the assertion of ALE. All accesses to V96SSC's internal registers are performed via the AD[15:0] lines. In 32-bit i960Jx systems, the internal registers are typically accessed in a 32 bit region where access to the internal registers is done by software 16 bits at a time (BTYPE="10"). Alternately, it can be mapped into a 16 bit region using BTYPE="11". While the V96SSC is internally a 16-bit device, it is capable of supporting 32-bit memory and peripheral devices. V96SSC also supports direct interface to PPC401Gx. When BTYPE="01" then the boot address matches that of the PPC401Gx. In this mode a cycle can be initiated with either an ALE or ADS pulse. Since the PPC401Gx has only an ALE output and lacks an ADS (AS) pin, ADS on the V96SSC can be tied high by a pull-up resistor.
2.2
Burst DRAM Controller
The V96SSC's DRAM controller provides the following features: * * * * * * * * * * Support for fast page mode, extended data out, and Ramtron's enhanced DRAM architectures Two DRAM banks of up to 64MByte each (128MBytes total) Programmable DRAM bank address base and size Programmable row/column multiplexing mode Programmable RASx and CASx timings Support for 16-bit and 32-bit DRAM arrays Support for extended burst cycles up to 256 bytes transactions in length Programmable page caching to eliminate RAS cycles for subsequent accesses to the same DRAM page Programmable refresh counter 1-0-0-0 read and 0-0-0-0 write performance at 33MHz
The burst DRAM controller is designed to support traditional fast page mode DRAMs (FPM), the new extended data out page mode DRAMs (EDO), and Ramtron's ultra high-performance enhanced DRAM (Ramtron EDRAM) devices. A wide variety of DRAM speeds and organizations may be 4
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accommodated due to the V96SSC's flexibility. Two DRAM banks are provided. Each bank has its own programmable address base and size. The mapping of memory address lines to row and column addresses is also programmable for each bank. The twelve mixed address lines (MA[11:0]) are shared by both banks. Each bank may be independently enabled and/or write protected. Both banks share a common DRAM signal timing generator that controls all DRAM timing parameters. DRAM array width can be set to either 16-bit or 32-bits; the V96SSC controls lane steering logic in mixed width systems. FPM, EDO, and Ramtron EDRAMs are a natural fit for burst bus processors such as i960 or PPC401Gx family. The V96SSC takes advantage of fast page mode accesses for every burst transaction, insuring the highest transfer rate possible. The V96SSC also supports extended burst peripherals, such as networking controllers, up to a maximum length of 64Byte data cycles. The DRAM controller also includes page cache management logic. This logic detects subsequent burst accesses within the same DRAM page, and eliminates the RAS precharge time and row address cycles for these accesses. Removing these cycles can reduce the average wait-state profile for many applications. The "aggressiveness" of the caching algorithm is programmable, and page caching can be completely disabled. The page size is programmable from 512 to 8192 bytes.
2.3
DMA Controller
Two independent DMA Channels are provided in the V96SSC. The DMA Controller generates fly-by cycles to transfer data directly from the DRAM to the selected peripheral, or vice-versa. Each channel includes a request input (DREQx), an acknowledge output (DACKx), and an end-of-process output (EOPx, accessible via the I/O Multiplexer). Each channel can also be assigned to a chip select/strobe channel to provide the necessary strobing signals to the DMA target/source peripheral. The DMA buffer start and stop addresses are programmable, as is the direction of transfer (read or write). Transfers may be initiated either via the DREQx pins or through software. The DMA Controller's programmable throttle count allows long transfers to be periodically interrupted to allow the processor access to the bus for code fetches, etc.
2.4
Serial Communications Unit (SCU)
The V96SSC's Serial Communications Unit offers both synchronous and asynchronous modes. In asynchronous mode, the Serial Communications Unit functions as an industry standard, full duplex UART. Transmission and reception are double buffered to help prevent data overruns. Interrupts are generated on receiver buffer full, transmit buffer empty, buffer overrun error, and framing error. In synchronous (SPI) mode, data is moved into, or out of, the SCU's buffers on transitions of the serial clock output pin (SCLK). Data word length is programmable from 1 to 16 bits. An interrupt is generated upon completion of an SPI transfer. SPI mode is ideal for connecting to serial interface peripherals such as A/D converters. The clock reference for the Serial Communications Unit can be either the independent baud rate generator or general purpose timer 1.
2.5
Chip Select/Strobe Unit
The Chip Select/Strobe Unit provides all the logic necessary to interface a wide array of peripherals and memory components to the i960Sx/Jx processor. Address decoding, wait-state generation, chipselect, and read/write strobe generation are handled completely by the V96SSC; no glue logic is
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needed. Eight output strobes/selects are available as output pins from the I/O Multiplexer. There are eight memory decode registers, each with the following options: * * * Base address and size (minimum granularity 64K) Region data width Read/Write enable
Each memory decode register has an associated Region Timing Control register. This register assigns timings for synchronous mode strobes as well as for wait-state generation. The following timings are programmable for each region: * Strobe assert from bus cycle start * Strobe de-assert from bus cycle start * READY delay from cycle start (wait-states) * Back-to-Back cycle delay Each of the 8 chip select/strobe output pins is assigned to one of four programmable memory ranges. These strobe signals can be used as asynchronous chip-selects, or combined with the timing values for the region to create read and write strobes. Each strobe has the following programmable options: * * * * Address match register assignment Access type: read, write, both Timing: asynchronous, synchronous Sub-decode: finer granularity decoding
The chip select/strobe unit is also tied to the DMA Controller. Each DMA channel can be assigned to a particular decode region and its associated timing.
2.6
General Purpose Timers (GPT)
Two identical 32-bit general purpose timers are integrated in the V96SSC. These timers may be used for a number of applications including: periodic interrupt generation, event counting, and pulse width modulation. The timers decrement every clock cycle, from a 32-bit preload value until a terminal count of zero is reached. A maskable interrupt is generated on terminal count. The timer may be programmed to halt on terminal count, or to reload and restart counting. Each timer has an external input (TIx) and external output pin (TOx). The TIx pin can be used as an edge or level sensitive start trigger. The TOx pin has the following modes: * * * * * Latched low Short and long pulse low on terminal count Toggle on terminal count Pulse width modulation One shot
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2.7 Watchdog and System Heartbeat Timers
The V96SSC's watchdog timer is used to recover a system that has crashed due to a software upset. If the watchdog timer is not periodically reset by "trusted" system software, the V96SSC assumes that a software crash has occurred and resets the processor by driving the RSTOUT pin low. The V96SSC's "system heartbeat" is a fixed-delay periodic interrupt to the processor that is used as a time reference by real-time operating systems.
2.8
Bus Watch Timer (BWT)
Additional system security is provided by the Bus Watch Timer. When enabled, the BWT monitors the READY pin (and, optionally, the PREADY pin) for every bus access initiated by an external master. If READY is not asserted within a programmable window (between 1 and 255 clocks), then the V96SSC will assert READY to end the cycle and generate an interrupt. For burst accesses, the BWT reloads its time-out count on each READY and returns to idle on BLAST.
2.9
Interrupt Control Unit
The Interrupt Control Unit manages interrupts for all off the V96SSC's on-chip interrupts, as well as providing interrupt control for up to 8 external requests. Each pending request is latched in the Interrupt Status Register. The Interrupt Mask Register allows independent masking of all interrupt sources. External interrupts may be routed to the Interrupt Control Unit via the I/O Multiplexer through the I/O port unit.
2.10 I/O Port Unit
The I/O Port Unit provides 8 independent single bit input or output ports. Each bit may be configured as an input port or an output port. As input ports, the unlatched inverted state of the associated pin is read from the Input Port Register. In addition, the input port bits are connected to the Interrupt Control Unit to provide external interrupt requests (IO[7:0] pins). When configured as an output port, the state of the associated pin is set by writing to the Output Port Register. The mapping of I/O Port bits to IOx pins is controlled via the I/O Multiplexer.
2.11 I/O Multiplexer
To allow the V96SSC to fit into a compact and economical 100-pin PQFP package, some nonessential I/O signals are multiplexed onto the IO[15:0] pins. Many internal signals have several options as to which IO pins they connect to. The multiplexing options for each IO pin are described in Table 4. Programming of the I/O Multiplexer is described in the V96SSC User's Manual.
2.12 Boot ROM Support
The V96SSC provides special support for boot ROM devices. When an access within the processor's boot range is detected on the A31, A[26:24] pins, the V96SSC outputs a latched low order address on the MA[11:0] pins (normally the muxed address lines for DRAM) and asserts IOC0. The V96SSC automatically detects boot ranges specific to each processor: 0x0000.0000 for the i960Sx, 0xFEFF.0000 for the i960Jx and 0xFFFF.0000 for PPC401Gx. For i960Sx systems using 8-bit boot ROMs, the V96SSC will automatically steer the byte data to the proper half of the AD bus (i960Jx processors handle byte assembly internally).
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3.0 Pin Description and Pinout
Table 3 below lists the pin types found on the V96SSC. Table 4 describes the function of each pin on the V96SSC. Table 5 lists the pins by pin number. Figure 2 shows the pinout for the 100-pin EIAJ PQFP package and Figure 3 shows the mechanical dimensions of the package.
Table 3: Pin Types
Pin Type I IS O O12 I/O ISU Input pin Schmidt trigger input pin Output pin with 4mA drive Output pin with 12mA drive I/O pin with 4mA output drive Schmidt trigger input with internal pull-up resistor Description
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Table 4: Signal Descriptions
Processor Interface Signals Signal Type Ra Description High-order address lines from i960 processor. These signals are latched internally by the V96SSC on the falling edge of ALE. Processor signals A[30:27] are optional and may be routed to the V96SSC through the I/O port pins (see below). Z Multiplexed address/data bus. For i960Jx based systems, the V96SSC only uses the lower 16-bits of the AD[31:0] bus. Address latch enable is connected to the i960 processor's ALE pin. This signal is connected to the internal address latches. Address status is connected to the AS pin on the i960Sx and to ADS on the i960Jx processors. Low order byte enables. The BE[1:0] pins are inputs for accesses from external masters; they become outputs when the V96SSC is the bus master. BE[3:2] are available through the I/O port pins for i960Jx systems (see below). End of burst indication from i960 processor. Z L Write/Read indication from the i960 processor. W/R is driven during V96SSC DMA operations to indicate the direction of the transfer. Hold request from the V96SSC DMA Controller to the i960 processor. Hold acknowledge from the i960 processor. This signal informs the V96SSC that it is now the local bus master. H Interrupt request output from the V96SSC interrupt controller. Data READY indication. The V96SSC returns READY to the i960 processor when data is read/written to memory addresses under the V96SSC's control. The V96SSC also monitors the READY signal for all bus accesses when the bus watch timer is enabled. Bus transaction type. These signals are examined during the assertion of AS, ADS or ALE to determine the type of external master initiating the bus cycle. BTYPE[1:0] I BTYPE[1:0] 00 01 10 11 Master i960SA/SB PPC401Gx i960JA/JD/JF (32-bit bus) i960JA/JD/JF (16-bit bus)
A31,A[26:16]
I
AD[15:0]
I/O
ALE
I
ADS
I
BE[1:0]
I/O
Z
BLAST W/R HOLD HLDA INT
I I/O O I O
READY
I/O
H
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Table 4: Signal Descriptions (cont'd)
DMA and DRAM Controller Signals Signal DREQ[1:0] DACK[1:0] MA[11:0] RAS[1:0] CAS[3:0] or CAL[3:0] WE LE OE[1:0] Type I O O12 O12 O12 O12 O12 O12 R DMA request inputs. Hb DMA acknowledge outputs. Xb DRAM multiplexed memory address lines. Hb DRAM row address strobes. Hb Column address strobes. In EDRAM mode, the CAS[3:0] signals become CAL[3:0]. Description
Hb Memory write enable. Hb Latch enable. Hb Memory output enables.
Multimode I/O Signals Each of these pins has two or more alternate functions. Pin function is controlled via the I/O multiplexer Signal IO0 IO1 Type I/O I/O R Z Z Description Functions: Input port 0, Output port 0, I/O strobe 0. Functions: Input port 1, Output port 1, I/O strobe 1, serial clock for serial communications unit in SPI mode. Functions: Input port 2, Output port 2, I/O strobe 2, serial data output (TxD in UART mode, SDO in SPI mode). Functions: Input port 3, Output port 3, I/O strobe 3, serial data input (RxD in UART mode, SDI in SPI mode). Functions: Input port 4, Output port 4, I/O strobe 4, refresh cycle indication from DRAM controller. Functions: Input port 5, Output port 5, I/O strobe 5, PREADY. Functions: Input port 6, Output port 6, I/O strobe 6, general purpose timer 0 input. Functions: Input port 7, Output port 7, I/O strobe 7, general purpose timer 1 input. Functions: Input port 0, Output port 0, general purpose timer 0 output. Functions: Input port 1, Output port 1, general purpose timer 1 output.
IO2
I/O
Z
IO3
I/O
Z
IO4 IO5 IO6
I/O I/O I/O
Z Z Z
IO7 IO8 IO9
I/O I/O I/O
Z Z Z
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Table 4: Signal Descriptions (cont'd)
Signal BE2/IO10 Type I/O R Z Description Functions: Input port 2, Output port 2, byte enable 2 input/output (for use w/32-bit masters), end-of-process indication for DMA channel 0. Functions: Input port 3, Output port 3, byte enable 3 input/output (for use w/32-bit masters), end-of-process indication for DMA channel 1. Functions: Input port 4, Output port 4, A27 input pin, general purpose timer 0 output. Functions: Input port 5, Output port 5, A28 input pin, general purpose timer 1 output. Functions: Input port 6, Output port 6, A29 input pin, end-of-process indication for DMA channel 0. Functions: Input port 7, Output port 7, A30 input pin, end-of-process indication for DMA channel 1.
BE3/IO11
I/O
Z
A27/IO12
I/O
Z
A28/IO13
I/O
Z
A29/IO14
I/O
Z
A30/IO15
I/O
Z
Clock, Reset and Configuration Signals Signal CLK2 RESET RSTOUT EN5Vc Type I IS O ISU L H R Description 2X clock input (in i960Jx/PPC401Gx systems, this signal is 2X the processor frequency). RESET input. RESET output from watchdog timer. Selects 5V (driven high) or 3.3V (driven low) DRAM memory interface. An internal weak pull-up is provided for backward compatibility.
Power and Ground Signals Signal VCC VCC3 GND Type R Description POWER leads for CPU I/O and internal core logic. Connect to a 5V board plane. POWER leads for DRAM interface signals. Connect to either a 5V or 3.3V board plane as determined by EN5V (5V only prior to revision B1). GROUND leads intended for external connection to a GND board plane.
-
a. R indicates state during reset. b. Reset state is 'Z' when 3.3V memory interface is selected via EN5V driven low. This feature can be used to float the DRAM signals for board testing. c. This signal was a no-connect prior to revision B1
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Table 5: Pin Assignments
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal READY ALE A22 A21 ADS RESET DREQ0 DREQ1 BTYPE0 BTYPE1 BLAST VCC GND W/R HOLD A20 A19 HLDA INT A18 A17 A16 RSTOUT CLK2 EN5V PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal BE0 BE1 AD0 VCC GND AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 VCC GND A30/IO15 A29/IO14 A28/IO13 PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal A27/IO12 BE3/IO11 BE2/IO10 IO9 IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 VCC3 GND3 MA0 MA1 MA2 MA3 RAS0 CAS0 VCC3 GND3 MA4 MA5 PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal MA6 MA7 RAS1 CAS1 VCC3 GND3 MA8 MA9 MA10 WE OE0 CAS2 LE VCC3 GND3 MA11 CAS3 OE1 DACK0 DACK1 A23 A24 A25 A26 A31
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Figure 2: Pinout for 100-pin EIAJ PQFP (top view)
100 READY ALE A22 A21 ADS RESET DREQ0 DREQ1 BTYPE0 BTYPE1 BLAST Vcc GND W/R HOLD A20 A19 HLDA INT A18 A17 A16 RSTOUT CLK2 EN5V BE0 BE1 AD0 Vcc GND 1
A31 A26 A25 A24 A23 DACK1 DACK0 OE1 CAS3 MA11 GND Vcc3 LE CAS2 OE0 WE MA10 MA9 MA8 GND 81 80 Vcc3 CAS1 RAS1 MA7 MA6 MA5 MA4 GND Vcc3 CAS0 RAS0 MA3 MA2 MA1 MA0 GND Vcc3 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 BE2/IO10 BE3/IO11 A27/IO12
V96SSC
(TOP VIEW)
30 31 50
51
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A28/IO13 A29/IO14 A30/IO15 GND Vcc AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1
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Figure 3: 100-pin EIAJ PQFP mechanical details
Unit of Measurement = millimeters
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V96SSC 4.0 DC Specifications
The following DC specifications are based on B1 stepping silicon.
Table 6: Absolute Maximum Ratings
Symbol VCC VIN IIN TSTG Parameter Supply voltage DC input voltage DC source or sink current Storage temperature range Value -0.3 to +7.0 -0.3 to VCC+0.3 -50 to +50 -65 to 150 Units V V mA C
Table 7: Guaranteed Operating Conditions
Symbol VCC TA Parameter Supply voltage Ambient temperature range Value 4.5 to 5.5 -40 to 85 Units V C
Table 8: DC Operating Specifications
Symbol VIL VIH IIL IIH VOL4 VOH4 VOL12 VOH12 IOZL IOZH Description Low level input voltage High level input voltage Low level input current High level input current Low level output voltage for 4mA outputs and I/O pins High level output voltage for 4mA outputs and I/O pins Low level output voltage for 12mA outputs and I/O pins High level output voltage for 12mA outputs and I/O pins Low level float input leakage High level float input leakage Conditions VCC = 4.75V VCC = 5.25V VIN=GND, VIN=5.25V VIN=VIN=5.25V IOL = 4mA IOH = -4mA IOL = 12mA IOH = -12mA VIN = GND VIN = VCC VCC = 5.5V Frequency = 20MHz VCC = 5.0V Frequency = 20MHz 3.7 -10 10 71 65 20 3.7 0.4 2.0 -10 10 0.4 Min Max 0.8 Units V V A A V V V V A A mA mA pF
ICC (max) Maximum supply current ICC (typ) CIO Typical supply current Input and output capacitance
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V96SSC 5.0 AC Specifications
The following AC specifications are based on A-0 stepping silicon.
Table 9: AC Test Conditions
Symbol VCC VIN COUT Parameter Supply voltage Input low and high voltages Capacitive load on output and I/O pins Limits 4.75 to 5.25 0.8 and 2.4 50 Units V V pF
Table 10: Capacitive Derating for Output and I/O Pins
Output Drive Limit 4mA 12mA Derating 0.11ns/pF for loads > 50pF 0.04ns/pF for loads > 50pF
Figure 4: Clock and Synchronous Signals
tCH tCL tC
CLK2 CLK
A31,A[26:16], BE[1:0]#, AS# BLAST#, BTYPE[1:0] W/R#, HLDA, DREQ[1:0]#
tSU tH
HOLD, DACK[1:0]# RSTOUT#, INT#
tCO
Figure 5: ALE Signal
tALE
ALE AD[15:0]
ADDRESS
tASU tAH
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Table 11: Clock, ALE, Synchronous Inputs and Outputs
33 MHz # 1 2 3 4 5 6 7 8 9 Symbol tC tCH tCL tSU tH tCO tALE tASU tAH Description CLK2 period CLK2 high time CLK2 low time Synchronous input setup Synchronous input hold CLK2 to synchronous output delay ALE pulse width Address setup to ALE falling Address hold from ALE falling 1 tC-7 3 1 Notes Min 15 6 6 10 3 12 Max Units ns ns ns ns ns ns ns ns ns
Notes: 1. tCO is for signals RSTOUT, HOLD, DACKx, and INT.
Figure 6: Internal Register Read/Write Waveforms
CLK2 CLK ADS A31,A[26:23] AD[15:0] W/R BLAST
tRZL tRLH tRHZ tOCHL OPORT ADDRESS VALID tAD0 ADDR ,,,DATA IN tADV ,,, tADH ADDRESS VALID tSU ADDR ,,,,, DATA OUT tH ,,,,,
READY IOC
OPORT
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V96SSC
Table 12: Timing Relationships for Internal Register Read/Write
33 MHz # 1 2 3 4 5 6 7 8 9 Symbol tADO tADV tADH tPD tOC tRZL tRLH tRHZ tRFV Description CLK2 to Data Output driving delay CLK2+ADS to internal register data valid, read access time Data hold after CLK2 IO asynchronous chip-select output delay IO synchronous strobe output delay from CLK2 READY float to driving low from CLK2 READY low to high delay from CLK2 READY high to float delay from CLK2 REFRESH (synchronous) output delay Notes Min Max Units 1 1 1 2 3 3 3 19 18 12 11 12 14 4 12 49 ns ns ns ns ns ns ns ns ns
Notes: 1. For V96SSC internal register read. 2. Delays are measured from address valid and ALE asserted. 3. In IOC mode, delays are measured from CLK2 when CLK is high and ADS is asserted. In OPORT mode, delays are measured from CLK2 when CLK is high during Td cycle.
Figure 7: Memory Timing Waveforms
CLK2 CLK A31,A[26:23] AD[15:0] MA[11:0] RAS CAS
tLEHL1 tLELH1 tLELH2 ADDR tARA ROW ADDR tDRAH ADDRESS VALID D In tRAH COL tCAV tDCAH ADDRESS VALID ADDR DATA OUT tCAH ROW ADDR COL
LE WE
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V96SSC Data Sheet Rev 2.3
Copyright (c) 1997, V3 Semiconductor Inc.
V96SSC
Table 13: Memory Interface Signals
33 MHz # 1 2 3 4 5 Symbol tARA tRAH tCAV tCAH tBCAH tBCAV Description Address input valid to row address valid on MA[11:0] Row address hold after CLK2 CLK2 to column address valid Column address hold after CLK2 or CLK2 Column address hold after CLK2 or CLK2 during burst operation CLK2 or CLK2 to column address valid during burst operation 1 1,2 1,2 4 4 Notes 1 3 12 Min Max Units 13 ns ns ns ns ns
6 7 8 9
1,2 3 4 1 1 1 1 1,5 1,6 1 1 1 1 1 1 1,7 1,7 tM+1 tN+1
14
ns ns ns
tDRAH DRAM row address hold tDCAH DRAM column address hold tRSHL CLK2 to RAS asserted delay
9 9 11 10 10 10 10 9 10 10 1 1 1 1
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10 tRSLH CLK2 to RAS de-asserted delay 11 tCHL1 CLK2 to CAS asserted delay
12 tCLH1 CLK2 to CAS de-asserted delay 13 tCHL2 CLK2 to CAS asserted delay 14 tCLH2 CLK2 to CAS de-asserted delay 15 tOEHL CLK2 to OE asserted delay 16 tOELH CLK2 to OE de-asserted delay 17 tWEHL CLK2 to WE asserted delay 18 tWELH CLK2 to WE de-asserted delay 19 tLEHL1 CAS asserted to LE asserted delay (read) 20 tLELH1 CAS de-asserted to LE de-asserted (read) 21 tLEHL2 CAS asserted to LE de-asserted delay (write) 22 tLELH2 CAS de-asserted to LE asserted (write)
Copyright (c) 1997, V3 Semiconductor Inc.
V96SSC Data Sheet Rev 2.3
19
V96SSC
Note: 1. The delay is from CPU Address valid or ALE if it comes first. Derate given delays by 0.058 ns per pF of load in excess of 50pF. 2. Relative to CLK2 only when T_CACA_RD or T_CACA_WR equals 0. 3. tM = (1 CLK2 period) * (T_RACA+1). 4. tN = (1/2 CLK2 period) * (T_CACA_RD + 1) for Read or (1/2 CLK2 period)*(T_CACA_WR+1) for 0-wait states write. 5. For Read Mode 2 and Write Mode 1 only. 6. For Write Mode 1 only. 7. For CAS Write Mode 0 and 1.
6.0 Revision History
Table 14: Revision History
Revision Number 2.3 2.2 2.1 2.01 Date 11/97 10/96 08/96 11/95 Comments and Changes First release of RevB1 data sheet. Data Book revision. Updated timing specification. Fixed incorrect polarity on some ALE and RESOUT signals. Fixed W/R description. Final Data Sheet. All specifications guaranteed from actual silicon. DC input levels changed to TTL compatible. Removed 16MHz and 20MHz timing specification. First released version of the data sheet. Some changes to AC and DC specifications and to waveforms. All future changes to the data sheet will be documented in detail in this section. First pre-silicon revision of preliminary data sheet. Sent only to a limited number of customers.
2.0
11/95
1.2
03/95
1.0
01/95
USA: 2348G Walsh Ave. Santa Clara CA 95051 Phone: (408)988-1050 Fax: (408)988-2601 Toll Free: (800)488-8410 (Canada and U.S. only) World Wide Web: http://www.vcubed.com
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V96SSC Data Sheet Rev 2.3
Copyright (c) 1997, V3 Semiconductor Inc.

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